Running Risk on FPGAs

Many models used in finance end up in formulation of highly mathematical problems. Solving these equations exactly in closed form is impossible as the experience in other fields suggests. Therefore, we have to look for efficient numerical algorithms in solving complex problems such as option pricing, risk analysis, portfolio management, etc. Computational finance, generally referring to the application of computational techniques to finance, has become an integral part of modeling, analysis, and decision-making in the financial industry.

In the past few years we have seen am increasing interest in the computational finance community for the application of Graphical Processing Units (GPUs). In this project we will explore the application of field-programmable gate arrays (FPGAs) for risk calculations. As test case we will consider the Incremental Risk Charge (IRC) application.

IIRC is intended to complement additional standards being applied to the value-at-risk modelling framework. Together, these changes address a number of perceived shortcomings in the current 99%/10-day VaR framework. Foremost, the current VaR framework ignores differences in the underlying liquidity of trading book positions. In addition, these VaR calculations are typically based on a 99%/one-day VaR which is scaled up to 10 days. The IRC represents an estimate of the default and migration risks of unsecuritised credit products over a one-year capital horizon at a 99.9 percent confidence level, taking into account the liquidity horizons of individual positions or sets of positions.